1. Field of the Invention
The technology described herein relates to non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397 and in U.S. Pat. No. 6,917,542; both of which are incorporated herein by reference in their entirety.
Typically, the program voltage applied to the control gate is applied as a series of pulses. The magnitude of the pulses is increased with each pulse by a predetermined step size. In the periods between the pulses, verify operations are carried out. That is the programming level of each cell being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than a verify level to which it is being programmed. One means of verifying the programming is to test conduction at a specific compare point.
Conduction represents an “on” state of the device corresponding to the flow of current across the channel of the device. An “off” state corresponds to no current flowing across the channel between the source and drain. Typically, a flash memory cell will conduct if the voltage being applied to the control gate is greater than the threshold voltage and the memory cell will not conduct if the voltage applied to the control gate is less than the threshold voltage. By setting the threshold voltage of the memory cell to an appropriate value, the memory cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a memory cell conducts current at a given set of applied voltages, the state of the memory cell can be determined.
Flash memory cells are erased by raising the p-well to an erase voltage (e.g. 20 volts) and grounding the word lines of a selected block (or other unit) of memory cells. The source and bit lines are floating. Erasing can be performed on the entire memory array, separate blocks, or another unit of cells. Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative.
One example of a non-volatile memory system suitable for implementing the present invention uses the NAND flash memory structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors, 100, 102, 104 and 106, in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line contact 126. Select gate 122 connects the NAND string to source line contact 128. Select gate 120 is controlled by applying the appropriate voltages to control gate 120CG. Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. Transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0. In one embodiment, transistors 100, 102, 104 and 106 are each memory cells. In other embodiments, the memory cells may include multiple transistors or may be different than that depicted in FIGS. 1 and 2. Select gate 120 is connected to select line SGD. Select gate 122 is connected to select line SGS.
FIG. 3 provides a cross-sectional view of the NAND string described above. As depicted in FIG. 3, the transistors of the NAND string are formed in p-well region 140. Each transistor includes a stacked gate structure that consists of a control gate (100CG, 102CG, 104CG and 106CG) and a floating gate (100FG, 102FG, 104FG and 106FG). The floating gates are formed on the surface of the p-well on top of an oxide or other dielectric film. The control gate is above the floating gate, with an inter-polysilicon dielectric layer separating the control gate and floating gate. The control gates of the memory cells (100, 102, 104 and 106) form the word lines. N+ doped layers 130, 132, 134, 136 and 138 are shared between neighboring cells, whereby the cells are connected to one another in series to form a NAND string. These N+ doped layers form the source and drain of each of the cells. For example, N+ doped layer 130 serves as the drain of transistor 122 and the source for transistor 106, N+ doped layer 132 serves as the drain for transistor 106 and the source for transistor 104, N+ doped layer 134 serves as the drain for transistor 104 and the source for transistor 102, N+ doped layer 136 serves as the drain for transistor 102 and the source for transistor 100, and N+ doped layer 138 serves as the drain for transistor 100 and the source for transistor 120. N+ doped layer 126 connects to the bit line for the NAND string, while N+ doped layer 128 connects to a common source line for multiple NAND strings.
Note that although FIGS. 1-3 show four memory cells in the NAND string, the use of four transistors is provided only as an example. A NAND string used with the technology described herein can have less than four memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
Each memory cell can store data represented in analog or digital form. When storing one bit of digital data, the range of possible threshold voltages of the memory cell can be divided into two ranges, which are assigned logical data “1” and “0.” In one example of a NAND flash memory, the voltage threshold is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage is positive after a program operation, and defined as logic “0.” When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
A memory cell can also store multiple states (known as a multi-state memory cell), thereby storing multiple bits of digital data. In the case of storing multiple states of data, the threshold voltage window is divided into the number of states. For example, if four states are used, there will be four threshold voltage ranges assigned to the data values “11,” “10,” “01,” and “00.” In one example of a NAND-type memory, the threshold voltage after an erase operation is negative and defined as “11.” Positive threshold voltages are used for the states of “10,” “01,” and “00.” In some implementations, the data values (e.g., logical states) are assigned to the threshold ranges using a Gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one bit will be affected. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the cell depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. patent application Ser. No. 10/461,244, “Tracking Cells For A Memory System,” filed on Jun. 13, 2003, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells.
Relevant examples of NAND-type flash memories and their operation are provided in the following U.S. patents/patent Applications, all of which are incorporated herein by reference in their entirety: U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935; 5,386,422; 6,456,528; and U.S. patent application Ser. No. 09/893,277 (Publication No. US2003/0002348).
Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. The foregoing two articles are incorporated herein by reference in their entirety. The programming techniques mentioned in section 1.2 of “Nonvolatile Semiconductor Memory Technology,” edited by William D. Brown and Joe E. Brewer, IEEE Press, 1998, incorporated herein by reference, are also described in that section to be applicable to dielectric charge-trapping devices.
Another approach to storing two bits in each cell has been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 4 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 4 includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248. Each string is connected to the source line by its select transistor (e.g. select transistor 230 and select transistor 250). A selection line SGS is used to control the source side select gates. The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common. Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242. Word line WL2 is connected to the control gates for memory cell 224, memory cell 244, and memory cell 252. Word line WL1 is connected to the control gates for memory cell 226 and memory cell 246. Word line WL0 is connected to the control gates for memory cell 228 and memory cell 248. As can be seen, each bit line and the respective NAND string comprise the columns of the array of memory cells. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array of memory cells.
In typical read and verify operations for NAND flash memory, the select gates (SGD and SGS) are raised to approximately 3 volts and the unselected word lines are raised to a read pass voltage (e.g. 5 volts) to make the transistors operate as pass gates. The selected word line is connected to a voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level. For example, in a read operation for memory cell 244, assuming a two level memory, the selected word line WL2 may be grounded so that it is detected whether the threshold voltage is higher than 0V and the unselected word lines WL0, WL1 and WL3 are at 5 volts. In a verify operation, the selected word line WL2 is connected to 1V, for example, so that it is verified whether the threshold voltage has reached at least 1V. The source and p-well are at zero volts. The selected bit lines are pre-charged to a level of, for example, 0.7V. If the threshold voltage is higher than the verify or read level applied to the selected word line, the potential level of the concerned bit line maintains the high level because of the non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line decreases to a low level, for example less than 0.5V, because of the conductive memory cell. The state of the memory cell is detected by a sense amplifier that is connected to the bit line.
FIG. 5 is a timing diagram that depicts the behavior of various signals during a read operation. Initially, all of the depicted signals are low. At time t1, the gate voltage (SGD) for the drain side select gate is raised to 1.5 to 4.5 volts to turn on the drain side select gate. It is assumed, in this example, that memory cell 244 is being read. The bit line BL_sel selected for reading (e.g., bit line for NAND string 204) is initially at zero volts. The unselected bit lines BL_unsel (e.g., bit lines for NAND strings 202 and 206) are set to zero volts. At time t2, the unselected word lines WL_unsel (e.g., WL0, WL1 and WL3) are raised to the read pass voltage (Vread) and the selected word line L_sel is raised to the read compare voltage (e.g., a voltage value to determine a read level or a verify level). At time t4, the selected bit line BL_sel is raised to a pre-charge value (e.g., 0.7 volts). At time t6, the gate of the source side select gate receive a voltage SGS of 1.5 to 4.5 volts so that the source side select gate will turn on, providing a path to ground. If the voltage applied on the selected word line WL_sel is greater than the threshold voltage of memory cell 244, the voltage on the bit line BL_sel will be dissipated via the source line. If the voltage applied on the selected word line WL_sel is not greater than the threshold voltage of memory cell 244, the voltage on the bit line BL_sel will be maintained. A sense amplifier is used to sense whether the bit line voltage was maintained or dissipated.
If the selected memory cell being read is in a programmed state, then the selected memory cell may not turn on during the process of ramping the word line to the read compare voltage. If the selected memory cell does not turn on while the ramping the selected word line to the read compare voltage, then as the unselected word lines ramp up to the read pass voltage (Vread), the source side (relative to the selected memory cell on the selected and unselected bit lines) of the NAND string channel is boosted up. Prior to turning on the source side select gate for the read/sensing operation, this boosted channel can result in hot electron injection in the region between the unselected memory cell (source side neighbor) and the selected memory cell, which over time may cause electrons to be injected into the floating gate of the memory cell that is the source side neighbor to the selected memory cell, thereby, raising the threshold voltage of that the source side neighbor. Experiments have shown that if the memory cells experienced many read operations (e.g., 100,000 or more) without a program or erase operation, the threshold voltage will increase over time. This behavior is called Read Disturb. In the above example of reading memory cell 244, memory cells along word line WL1 may experience this type of Read Disturb. This behavior can occur on the selected and unselected bit lines, but is worse on the unselected bit lines. This phenomenon is likely to be linked to the shrinking size of the flash memory devices.
Similarly, if turning on the drain side select gate is used to trigger a reading of the memory cell, rather than SGS, then the drain side of the NAND string channel will be boosted and can cause Read Disturb on the drain side neighbor to the selected memory cell.
There are some applications that may need to be able to perform many read operations without performing an intervening program or erase operation. For example, there are computing devices that use flash memory to store BIOS code. In some cases, the BIOS code is programmed once and then read many times at power-up and/or reset. Thus, the BIOS code may be subject to Read Disturb.
Additionally, some handheld computing devices and mobile telephones use flash memory to store operating system code. This code is typically written once and read many times. It is common for these devices to read the operating system code each time the device turns on. In some cases, the device (the entire device, the processor, or the memory system) may turn off after a predetermined amount of inactivity in order to minimize battery usage. When the device is used again, the relevant components power back on and the operating system code is read again. Thus, it is possible that for a frequently used device (e.g. used for a business), the operating system code is read many times a day. If the device is used long enough, the memory storing the operating system code may be subject to errors due to Read Disturb, causing the operating system code to be corrupted.
Additionally, flash memory is being used with trusted memory cards that require reading keys for authentication. Such devices typically write a key once and then read that key many times. If the card is used long enough, the memory storing the key may be subject to errors due to Read Disturb, causing the key to be corrupted.
Some previously implemented attempts to avoid Read Disturb include using ECC to correct errors, periodically refresh the data by performing a programming operation or periodically re-writing the data to another location. These solutions, however, may require extra hardware or may negatively impact performance.